The present disclosure relates to a column redundancy circuit, and more particularly to a column redundancy circuit for preventing a control signal associated with a row path from being toggled, using a refresh signal with an enable width adjusted, so as to reduce current consumption in a refresh mode.
In general, a dynamic random access memory (DRAM) comprises a unit cell which is composed of one switching transistor and one storage capacitor. As a result, different from a static random access memory (SRAM) or flash memory, the DRAM may be subject to a phenomenon in which data stored in the cell is lost due to leakage current with the lapse of time. In order to prevent this phenomenon, the data stored in the cell is externally written into the cell again at regular time intervals. This operation is called a refresh. The refresh is performed in such a manner that each word line is selected at least once within a retention time of each cell of a memory cell array, and data of each cell connected to the selected word line is sensed and amplified and then rewritten into the cell. Here, the retention time refers to a time for which data can be retained in a cell with no refresh after being written in the cell.
The refresh is generally performed with respect to a row address which is generated by an internal counter in response to a refresh command. Thus, the refresh can be carried out by merely changing only the row address, so that there is required no operation of a column path in a refresh mode.
On the other hand, when a defect occurs in some memory cells in a memory device, the chip typically does not operate in the expected manner. In this case, a repair operation is performed which replaces a memory cell determined through testing_to be defective with a redundant memory cell formed in advance. In this repair operation, a column repair operation which is performed through a column redundancy circuit may employ, when a fail occurs in a specific cell, a scheme for repairing the specific cell, including even all other cells not failed, as shown in FIG. 7, or a scheme for column-repairing only cells of a failed block as shown in FIG. 8.